As the critical dimension of the semiconductor device is getting smaller continuously, the size of the contact hole (CA) is also getting smaller and smaller, and the distance between the gate and the contact hole also reduces accordingly.
One of the projects that major semiconductor corporations and research organizations all over the world compete to research and develop is the gate engineering research of CMOS device. In general, as shown in FIG. 1, a gate stack structure comprises a gate dielectric layer 20 formed on a substrate 10, a gate 40 formed on the gate dielectric layer 20, and a sidewall spacer 30 surrounding the gate dielectric layer 20 and the gate 40. The gate 40 mostly uses a metal gate. As shown in FIG. 2, the gate 40 is located on an active region 12 and a connection region 14 of the substrate 10. The gate 40 located on the active region 12 is used to adjust the device performance, and the gate 40 located on the connection region 14, the contact hole 16 formed on the connection region 14 as well as the contact hole 18 formed on the active region 12 are used to form a metal interconnection.
As shown in FIG. 3, after forming the gate stack structure, a first contact hole 60 that is of the same height as the gate stack structure is formed, then a second contact hole 62 is formed on the first contact hole 60 (the second contact hole 62 and the first contact hole 60 together forming the contact hole in the same interlayer dielectric layer 50) so as to form a first layer of metal interconnection. The process of forming the contact hole is divided into two steps (which is simply referred to as dual-contact-hole process herein) to facilitate the reduction of the depth-to-width ratio of the contact hole during the etching, thereby reducing defects such as incomplete etching and hole filling.
However, in the above-mentioned process, with reference to FIGS. 1 and 2, the second contact hole 62 is very close to the gate 40 located on the active region 12, so short-circuit is prone to occur between the second contact hole 62 and the gate 40 in practice owing to limitation of the process (as indicated by dashed line 64 in FIG. 3).